Conventional methods of fabricating complementary metal oxide semiconductor (CMOS) field effect transistors may include formation of stress liners, which operate to increase electron and hole mobility in NMOS and PMOS field effect transistors, respectively. One such method is disclosed in U.S. Pat. No. 7,297,584 to Park et al., entitled “Methods of Fabricating Semiconductor Devices Having a Dual Stress Liner.” In particular, the '584 patent to Park et al. discloses a dual stress liner, including a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. Additional techniques to use stress to increase free carrier mobility in NMOS and PMOS devices are disclosed in US 2005/0218455 to Maeda et al., entitled “Low Noise and High Performance LSI Device, Layout and Manufacturing Method.”
Techniques to form high-stress silicon nitride films for strained silicon technologies that use UV curing are also disclosed in an article by Y. Miyagawa et al., entitled “Local Bonding Structure of High-Stress Silicon Nitride Film Modified by UV Curing for Strained Silicon Technology Beyond 45 nm Node SoC Devices,” Jpn. J. Appl. Phys., Vol. 46, pp. 1984-1988 (2007), and in US 2008/0142902 to Chen et al., entitled “Method for Fabricating Ultra-High Tensile-Stressed Film and Strained-Silicon Transistors Thereof.”
Conventional CMOS fabrication techniques may also include steps to improve contact resistance by forming silicide contact regions on gate and source/drain regions of MOS transistors. As disclosed in JP 2007-281318 to Akihiro Shimizu et al., a laser annealing technique may be used to improve quality of nickel silicide films in MOSFET devices.